Faithful Modification

The process of raising the strength of a weak signal without any change in its
general shape is known as faithful modification.
The proposition of transistor reveals that it'll serve duly if its input circuit ( i.e.
base- emitter junction) remains forward prejudiced and affair circuit ( i.e. collector- base
junction) remains rear prejudiced at all times. This is also the crucial factor for achieving
faithful modification.

To insure this, the following introductory conditions must be satisfied:

( i) Proper zero signal collector current.
(ii) Minimal proper base-emitter voltage (V _BE) at any moment.
(iii) Minimal proper collector-emitter voltage (V _CE) at any moment.
The conditions (i) and (ii) insure that base-emitter junction shall remain duly
forward Poisoned during all corridor of the signal. O n the other hand, condition (iii) ensures. That base-collector junction shall remain duly rear poisoned at all times. In other
word, the fulfillment of these conditions will insure that transistor works over the active
. region of the affair characteristics i.e. between achromatism to cut off.

(i) Proper zero signal collector current. consider an npn transistor circuit
shown inFig. 1 (i). During the positive half- cycle of the signal, base is positivew.r.t.
emitter and hence base-emitter junction is forward poisoned. This will beget a base
current and much larger collector current to inflow in the circuit. The result is that positive half- cycle of the signal is amplified in the collector as shown.

Still, during the
. negative half- cycle of the signal, base-emitter junction is rear prejudiced and hence no
. current folows in the circuit. The result is that there's no affair due to the negative half-
cycle of the signal. Therefore we shall get an amplified affair of the signal with its negative
half- cycles fully cut off which is treacherous modification.

Now introduce a battery source V BB in the base circuit as shown in Fig-1 (ii).

The magnitude of this voltage should be similar that it keeps the input circuit forward
prejudiced indeed during the peak of negative half- cycle of the signal. When no signal is apply,a.d.c. current I C will flow in the collector circuit due to V BB as shown.
This is know as zero signal collector current I C. During the positive half- cycle of the signal,
. input circuit is more forward prejudiced and hence collector current increases. Still,
. during the negative half- cycle of the signal, the input circuit is less forward prejudiced and
. collector current diminishments. In this way, negative half- cycle of the signal also appears in
.the affair and hence faithful modification results. It follows, thus, that for faithful
. modification, proper zero signal collector current must flow. The value of zero signal
collector current should be at least equal to the maximum collector current due to signal
alone i.e.

Zero signal collector current Max. collector current sue to gesture alone.
Illustration. Suppose a signal applied to the base of a transistor gives a peak
collector current of 1 mama. Also zero signal collector current must be at least equal to
1mA so that indeed during the peak of negative half- cycle of the signal, there's no cut off
.as shown in Fig-2 (i).
Still, say 0, If zero signal collector current is less.5 mama as shown in Fig. 2 (ii), also
. Some part (should portion) of the negative half- cycle of signal will be cut off in the
affair.

(ii) Proper minimal base-emitter voltage. In order to achieve faithful
modification, due base-emitter voltage (V _BE) shouldn't fall below 0.5 V for germanium
transistors and0.7 V for Si transistors at any moment.

The base current is veritably small until the * input voltage overcomes the implicit
hedge at the base-emitter junction. The value of this implicit hedge is 0.5 V for Ge
transistors and 0.7 V for Si transistors as shown in Fig-3 Once the implicit hedge is
overcome, the base current and hence collector current increases sprucely. Thus, if
. base- emitter voltage V BE falls below these values during any part of the signal, that part will be amplified to lower extent due to small collector current.

This will affect in treacherous modification.

( iii) Proper minimum V_CE at any moment. For faithful modification, the
collector-emitter voltage V_CE shouldn't fall below 0.5 V for Ge transistors and 1 V for silicon transistors. This is called knee voltage ( See Fig. 4).

In practice,a.c. signals have small voltage position (<0.1 V) and if applied directly
will not give any collector current.

When V _CE is too low ( lower than0.5 V for Ge transistors and 1 V for Si transistors),
. The collector- base junction isn't duly rear prejudiced. Thus, the collector

can not attract the charge carriers emitted by the emitter and hence a lesser portion of
them goes to the base. This decreases the collector current while base current increases.
Hence, value of cascade. Thus, if V _CE is allowed to fall below V knee during any part of the signal, that part will be less amplified due to reduced.

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